(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure of a static type memory cell having a high resistance to soft errors.
(2) Description of the Related Art
Since the capacity of semiconductor memories is becoming large, the area of a static type memory cell is required to be as small as possible. From this viewpoint, memory cells have changed from CMOS type memory cells to resistor type memory cells. A CMOS type memory cell is constituted by a flip-flop made of p-channel and n-channel MOS transistors, whereas a resistor type memory cell (constituted by a flip-flop made of an n-channel transistor and a resistor) replaces a p-channel MOS transistor by a resistor to reduce the memory cell size. With recent technology advancement, a three-dimensional memory cell, that is, TFT (Thin Film Transistor) type memory cell is available which has a p-channel thin film transistor formed on an n-channel MOS transistor, and the memory cell size is further reduced. As compared to a resistor type memory cell, a TFT type memory cell requires a number of manufacturing processes. For this reason, TFT type memory cells and resistor type memory cells are selectively used depending on their application fields.
A resistor type memory cell will be described in the following as one example of conventional static type memory cells.
FIG. 1 is an equivalent circuit diagram of a static type memory cell. Resistor elements R1 and R2 of high resistance are used as load elements, and drive MOS transistors Q1 and Q2 are used as drive elements. One end of each resistor element is connected to a power source voltage Vcc, and the source of each drive MOS transistor is connected to a ground potential Vss. These resistor elements and drive transistors constitute a flip-flop circuit. Data is stored at information storage nodes N1 and N2 of the flip-flop circuit. Parasitic capacitors C1 and C2 are formed at the information storage nodes. For reading and writing data to and from the flip-flop circuit, the nodes are connected respectively to bit lines BL and BL' via transfer MOS transistors Q3 and Q4 to be selected by a word line WL.
The structure of such a conventional memory cell will be described with reference to FIGS. 2A, 2B, and 3. FIGS. 2A and 2B are plan views of a conventional memory cell. FIG. 2A is a plan view after drive and transfer MOS transistors are formed, and FIG. 2B is a plan view after resistor elements and bit lines are formed. FIG. 3 is a cross sectional view showing the vertical structure of this memory cell, the cross section being taken along line 3--3 of FIGS. 2A and 2B.
As shown in FIG. 2A, on the surface of a silicon substrate of a p-conductivity type or on the surface of a p-well formed in the silicon substrate, silicon active regions 102 and 102a are formed surrounded by an element isolation insulating film 101. Drive gate electrodes 103 and 103a for driving the drive MOS transistors are connected via buried contact holes 104 and 104a to the silicon active regions 102 and 102a. Word lines 105 and 105a are formed, the lines also serving as transfer gate electrodes for driving the transfer MOS transistors.
The source and drain regions of the drive and transfer MOS transistors are formed by implanting impurity ions such as arsenic ions into a region at which the gate electrodes are not formed in the silicon active regions. Thereafter, an interlayer insulating film is deposited covering the whole surface of the substrate. Ground contact holes 106 and 106a are formed in this interlayer insulating film as shown in FIG. 2B. The source regions of the drive transistors are electrically connected to a ground interconnect 107 via the contact holes.
Next, node contact holes 108 and 108a are formed as shown in FIGS. 2A and 2B. High resistance elements 109 and 109a are formed which are electrically connected to the drive gate electrodes 103 and 103a via the contact holes 108 and 108a. Interconnects 110 and 110a for applying a voltage to these high resistance elements 109 and 109a are also formed.
After bit line contact holes 111 and 111a are formed, bit lines 112 and 112a are formed to complete the structure of a conventional static type memory cell.
Methods of improving the resistance to soft errors have been proposed. These methods improve the resistance to soft errors by increasing the capacitance values of the parasitic capacitors C1 and C2 at the information storage nodes N1 and N2 of the memory cell having the structure described above. As one example of such methods, technology disclosed in Japanese Patent Application Kokai Publication No. Hei 2-116162 will be described with reference to the cross sectional structure of the memory cell shown in FIG. 3.
As shown in FIG. 3, a p.sup.+ -type buried layer 202 is formed on the surface of a p-type semiconductor substrate 201 at a predetermined region. A p-type epitaxial layer 203 is deposited thereon. Next, an element isolation insulating film 204 is formed on the surface of the p-type epitaxial layer 203 at a predetermined region.
Thereafter, a transfer transistor is formed having n.sup.+ -type diffusion layers 205 and 205a as its source/drain regions, a gate insulating film 206, and a transfer gate electrode 207. A drive gate electrode 208 is connected to the p-type epitaxial layer 203 via the buried contact hole, and an n.sup.+ -type diffusion region 209 is connected to the n.sup.+ -type diffusion region 205, reaching the p.sup.+ -type buried layer 202. Therefore, a p-n junction made of high concentration impurities is formed at the interface between the n.sup.+ -type diffusion region 209 and the p.sup.+ -type buried layer 202. This p-n junction increases the values of the parasitic capacitor C1 or C2.
Next, a first interlayer insulating film 210 and a ground interconnect 211 are formed, and a second interlayer insulating film 212 is deposited to cover them. A node contact hole 213 is then formed in the second interlayer insulating film 212 at a position preset for the drive gate electrode 208. A high resistance element 214 and a high resistance interconnect 214a are formed, which are connected to the drive gate electrode 208 via the node contact hole 213. A bit line 217 is formed connecting via a bit line contact hole 216 to the n.sup.+ -type diffusion layer 205a. In the above manner, the fundamental structure of a static type memory cell is formed.
A memory cell described above is associated, however, with the following disadvantages as the memory cell size is made small for aiming at large capacitance and high integration.
Uranium (U) or thorium (Th) contained in very small amount in ceramic material used for sealing a semiconductor device or interconnect material radiates .alpha.-rays when it decays. As .alpha.-rays are incident on a memory cell, electron-hole pairs are generated along the path of .alpha.-rays and mixed with charges stored in an information storage node. If a semiconductor element is so small that its memory data cannot be held, stored data is easily destroyed.
A conventional static type memory cell is designed to store charges sufficient for compensating for a loss of charges to be caused by .alpha.-rays, by the capacitance of the p-n junction between the n.sup.+ -type diffusion layer and p-type semiconductor substrate (or p-well) of a drain region of a MOS transistor and a dielectric capacitance of the gate insulating film. Another countermeasure for .alpha.-rays is to form a high impurity concentration buried layer just under a memory cell to thin a depletion layer and increase junction capacitance. However, these countermeasures become unsatisfactory in compensating for a loss of charges to be caused by .alpha.-rays if the memory cell area becomes small. As the memory cell structure becomes finer, a soft error rate increases and the reliability of semiconductor devices is considerably lowered.
According to the above-described technology of Japanese Patent Application Kokai Publication No. Hei 2-116162, a high impurity concentration buried layer is formed under a memory cell and connected to the drain diffusion layer of the drive MOS transistor. Therefore, since a diffusion region constituting the high impurity concentration buried layer and the p-n junction is formed, the parasitic capacitance at an information storage node of the memory cell is increased.
With this technology, although the resistance to soft errors can be improved to a certain degree, the manufacturing processes increase in number and becomes complicated because of the formation of a high impurity concentration buried layer. Furthermore, as the memory cell becomes finer, the area of the p-n junction reduces, thus making it difficult to secure sufficient parasitic capacitance.